The invention relates to auto-zeroing circuits, and more specifically to an auto-zeroing circuit that compensates for both offset of an amplifier and gain linearity error of the amplifier, without use of complex, multiple-stage, high gain circuitry in the amplifier.
By way of background, auto-zeroing techniques, also referred to as correlated double sampling techniques, are commonly used in high precision switched capacitor circuit designs to minimize offset errors and low frequency errors. Ordinarily, a "gained up" offset error of the main amplifier is stored on a capacitor which then is sampled by an auxiliary amplifier. The output of the auxiliary amplifier is applied as an auxiliary input to the main amplifier to force an internal correction of the offset error.
However, another error source in a switched capacitor circuit design is non-linear gain of the operational amplifier. This can be described with reference to the prior art circuit shown in FIG. 4, which is described in "A Micropower CMOS-Instrumentation Amplifier", by M. Degrauwe et al., IEEE Journal of Solid-State Circuits, Vol. SC20, No. 3, June 1985, pp 805-807. Referring to FIG. 4, a switched capacitor sampling stage including capacitor C1 and switches S1, S2, and S5 couples V.sub.IN to a summing node 12 connected to the (-) input of a main amplifier 3 having a gain A1. A switched capacitor network including capacitor C2 and switches S8 and S9 is coupled between summing node 12 and output conductor 19 of main amplifier 3, on which V.sub.OUT is produced. A switch S12 couples output conductor 19 to a subsequent stage (not shown). An auxiliary amplifier 13 having gain A2 has its output coupled to an adjustment input of main amplifier A1. The (+) input of auxiliary amplifier 13 is connected to one plate of a capacitor C4, the other plate of which is connected by fixed reference voltage conductor 23 to the (+) input of auxiliary amplifier A2. Typically, the gain A1 is not constant, but varies with V.sub.OUT. That causes distortion of V.sub.OUT relative to V.sub.IN.
.phi.1 and .phi.2 are non-overlapping clock signals, .phi.2 being a sampling phase in which V.sub.IN is sampled onto capacitor C1 and feedback capacitor C2 is reset. .phi.1 is a charge transfer phase during which V.sub.IN is amplified by approximately the ratio of C1 to C2 at the output of main amplifier 3. .phi.1 is also the phase during which the output voltage V.sub.OUT is sampled by the following stage (not shown). During each .phi.2 phase, the (+) and (-) inputs of main amplifier 3 are short circuited together, so that the value of V.sub.OUT during .phi.2 is a correction voltage approximately equal to V.sub.OS .multidot.(A1/A2), where V.sub.OS is the input offset voltage of main amplifier 3. The correction voltage is always "referenced to a fixed reference voltage", meaning that the feedback through auxiliary amplifier 13 keeps V.sub.OUT close to the fixed reference voltage. Switch S11 is closed, so that correction voltage is stored on capacitor C4 and causes auxiliary amplifier 13 to produce a correction current or voltage in an auxiliary input to main amplifier 3 so as to cancel the input offset voltage V.sub.OS thereof. The same correction voltage V.sub.OS .multidot.(A1/A2) is stored on capacitor C4 during every .phi.2 phase, and during every .phi.1 phase auxiliary amplifier 13 applies the same correction current or voltage to the auxiliary input of main amplifier 13 to cancel the effect of V.sub.OS. Unfortunately, since the gain A1 is non-linear, A1 has a different value when V.sub.OUT is close to zero than if V.sub.OUT has a relatively high value. This produces undesired distortion in the value of V.sub.OUT.
Traditionally, such non-linear gain error is reduced by providing large, open loop gain in the main amplifier. However, that usually requires an expensive, multi-stage amplifier of complex design. Known finite gain compensation techniques are used to suppress distortion error due to non-linear amplifier gain.